PCI1420 Datasheet, PDF (92/137 Pages) Texas Instruments – PC Card Controllers

4.50 Serial Bus Control and Status Register
The serial bus control and status register communicates serial bus status information and select the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 4–25 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Serial bus control and status
Type
R/W
R
R
R
R/C
R/W
R/C
R/C
Default
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Serial bus control and status
Read-only, Read/Write, Read/Write to Clear
B3h (function 0)
00h
Table 4–25. Serial Bus Control and Status Register
BIT
SIGNAL TYPE
FUNCTION
Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte
7
PROT_SEL R/W protocol is used on read commands. The word address byte in the serial bus index register (see
Section 4.48) is not output by the PCI1420 when bit 7 is set.
6
RSVD
R Reserved. Bit 6 returns 0 when read.
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
5
REQBUSY
R
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see
Section 4.49). Bit 5 must be polled on reads from the serial interface. After the byte read access has been
requested, the read data is valid in the serial bus data register.
Serial EEPROM Busy status. Bit 4 indicates the status of the PCI1420 serial EEPROM circuitry. Bit 4 is set
4
ROMBUSY
R
during the loading of the subsystem ID and other default values from the serial bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected. A pulldown resistor
must be implemented on the LATCH terminal for bit 3 to be set. If bit 3 is reset, then the MFUNC4 and
3
SBDETECT R/C MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs.
0 = Serial bus interface not detected
1 = Serial bus interface detected
2
SBTEST
 ^{Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.}
R/W
0 = Serial bus clock at normal operating frequency, 100 kHz (default)
1 = Serial bus clock frequency increased for test purposes
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
1
REQ_ERR
R/C
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1.
0 = No error detected during user requested byte read or write cycle
1 = Data error detected during user requested byte read or write cycle
EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the
auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on
0
ROM_ERR
R/C
invalid EEPROM data formats. See Section 3.6.1, Serial Bus Interface Implementation, for details on
EEPROM data format. Bit 0 is cleared by a write back of 1.
0 = No error detected during auto-load from serial bus EEPROM
1 = Data error detected during auto-load from serial bus EEPROM
4–36