TMS320C1X Datasheet, PDF (91/146 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C – JANUARY 1987 – REVISED JULY 1991
In addition to the above timings, t_v must be taken into account. t_v is the time that the data bus is
guaranteed to be held after the rising edge of MWE or IOWE. In other ′C1x devices, the value of t_v was
referenced to CLKOUT↓ and not WE↑ (see Figure 12). For the ′C16, t_v is a minimum of 5 ns. This implies
that MWE and IOWE must be tied directly to the external device. If required, decode logic must be added
to an input other than the read/write input — for example, the chip select on SRAMs. If the external device
does not have two inputs, then transparent latches must be added to extend the time data is held on the
data bus. These latches must be off the bus prior to the next instruction (see Figure 12).
CLKOUT
MWE or IOWE
D15-D0
tv
td10
Figure 12.
where:
t_v = 5 ns (min)
t_d10 = 15 ns (max)
There is a potential for bus conflict on the prefetch and execution of a TBLW or an OUT instruction. Figure 13
details the timings to be considered. In addition to the timings for the ′C16, timing definitions for interface are
also included.
Dummy Prefetch Cycle
CLKOUT
MEN
CE
TBLW or OUT Execution
tddeco
tdmemh
D15-D0
Memory Driven Data
D15-D0
DSP Driven Data
td9(MEN)
tconf
where:
Figure 13.
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