TMS320C5514 Datasheet, PDF (90/138 Pages) Texas Instruments – TMS320C5514 Fixed-Point Digital Signal Processor

TMS320C5514
SPRS646 – JANUARY 2010
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Table 5-18. Timing Requirements for EMIF Asynchronous Memory⁽¹⁾ (see Figure 5-17, Figure 5-19, and
Figure 5-20)
CV_DD = 1.3 V
NO.
DV_DDEMIF = 3.3/2.8/2.5/1.8 V
UNIT
MIN
NOM
MAX
READS and WRITES
2 t_{w(EM_WAIT)}
Pulse duration, EM_WAITx assertion and deassertion
2E
ns
READS
12 t_{su(EMDV-EMOEH)} Setup time, EM_D[15:0] valid before EM_OE high
11
ns
13 t_{h(EMOEH-EMDIV)} Hold time, EM_D[15:0] valid after EM_OE high
0
ns
14 t_{su (EMOEL-EMWAIT)} Setup Time, EM_WAITx asserted before end of Strobe Phase⁽²⁾
4E + 7.5
ns
WRITES
26 t_{su (EMWEL-EMWAIT)} Setup Time, EM_WAITx asserted before end of Strobe Phase⁽²⁾
4E + 7.5
ns
(1) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of
the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100/120 MHz, E =
10/8.33 ns, respectively.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-19 and Figure 5-20 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
90
Peripheral Information and Electrical Specifications
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