XIO1100GGB Datasheet, PDF (9/36 Pages) Texas Instruments – PCI Express 1.1 Compliant

Description
2.8.1 8B/10B Decode Error
When XIO1100 detects an 8B/10B decode error, it asserts an EDB (0xFE) symbol in the data on the
RX_DATA[15:0] where the bad byte occurred (only the erroneous byte is replaced with the EDB symbol; the
other byte is still valid data). In the same RX_CLK clock cycle that the EDB symbol is asserted on the
RX_DATA[15:0] bus, the 8B/10B decode error code (100b) is asserted on the RX_STATUS[2:0] bus. Since
the 8B/10B decoding error has priority over all other receive error codes, it could mask out a disparity error
occurring on the other byte of data being clocked onto the RX_DATA[15:0] with the EDB symbol.
2.8.2 Elastic Buffer Overflow Error
When the elastic buffer overflows, data is lost during reception. XIO1100 generates an elastic buffer overflow
error when this occurs. The elastic buffer overflow error code (101b) is asserted on the RX_STATUS[2:0] on
the RX_CLK clock cycle that the omitted data would have been asserted. The remaining data asserted on the
RX_DATA[15:0]] bus is still valid data, but the elastic buffer overflow error code on the RX_STATUS[2:0] just
marks a discontinuity point in the data stream being received.
2.8.3 Elastic Buffer Underflow Error
When the elastic buffer underflows, EDB (0xFE) symbols are inserted into the data stream on the
RX_DATA[15:0] bus to fill the holes created by the gaps between valid data. For every RX_CLK clock cycle,
an EDB symbol is asserted on the RX_DATA[15:0] bus, and an elastic buffer underflow error code (111b) is
asserted on the RX_STATUS[2:0] bus.
2.8.4 Disparity Error
When the XIO1100 detects a disparity error, it asserts a disparity error code (111b) on the RX_STATUS[2:0]
bus in the same RX_CLK clock cycle that it asserts the erroneous data on the RX_DATA[15:0] bus. However,
it is not possible to discern which byte had the disparity error.
2.9 Loopback
The XIO1100 begins a loopback operation when the MAC asserts TX_DET_LOOPBACK while holding
TX_ELECIDLE de−asserted. The XIO1100 stops transmitting data to the TXP/TXN signaling pair from the
TI−PIPE interface and begins transmitting the data received at the RXP/RXN signaling pair on the TXP/TXN
signaling pair. This data is not routed through the 8B/10B coding/encoding paths. While in the loopback
operation, the received data is still sent to the RXDATA[15:0] bus of the TI−PIPE interface. The data sent to
the RXDATA[15:0] bus is routed through the 10B/8B decoder. The XIO1100 terminates the loopback operation
and returns to transmitting TXDATA[15:0] over the TXP/TXN signaling pair when the TX_DET_LOOPBACK
signal is de−asserted.
2.10 Electrical Idle
The XIO1100 expects the MAC to issue the required COM (K28.5) symbol and the required number of IDL
symbols (K28.3) on TXDATA[7:0] before asserting the TX_ELECTRICAL signal. The XIO1100 meets the
requirements of the Electrical Requirements of a PCI Express PHY (for these requirements, see Section
4.3.1.9, Electrical Idle, and Table B−2 in Appendix B of PCI Express Base Specification Revision 1.1).
2.11 Polarity Inversion
Polarity inversion can happen in many places in the receive chain, including somewhere in the serial path,
as symbols are placed into the elastic buffer or as symbols are removed from the elastic buffer. The XIO1100
inverts the data received on the RXP/RXN signaling pair when RxPolarity is asserted. The inverted data will
begin showing up on the RXDATA within 20 RX_CLKS of when RxPolarity is asserted.
2.12 Setting Negative Parity
To set the running disparity to negative, TxCompliance is asserted for one clock cycle that matches with the
data that is to be transmitted with negative disparity.
June 2006 Revised August 2011
SLLS690C
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