TRF4903 Datasheet, PDF (9/26 Pages) Texas Instruments – SINGLE-CHIP MULTIBAND RF TRANSMITTER

TRF4903
SINGLEĆCHIP MULTIBAND RF TRANSMITTER
timing data for DCLK and TX_DATA
tsu(TX)
th(TX)
PARAMETER
Setup time, TX_DATA valid before DCLK ↑
Hold time, TX_DATA valid after DCLK ↑
Transmit
tsu(TX)
TX_DATA
Input
SWRS023B − MAY 2004 − REVISED MARCH 2005
th(TX)
MIN TYP MAX UNIT
100
ns
100
ns
DCLK
Output
TSK =
1
fc
NOTE: TX_DATA is latched at the rising edge of DCLK.
Figure 3. Timing Data for DCLK and TX_DATA
If transmit capture mode is selected (by setting bit 15 in word E), the data transitions (high-to-low or low-to-high)
on the TXDATA pin is timed to coincide with the falling edge of DCLK. Any microcontroller using the TRF6903
can then latch TXDATA on the rising edge of DCLK. For more details, see the data clock section.
detailed description
bit synchronizer and data clock
When enabled, the integrated bit synchronizer and data clock circuitry provide as an output at terminal 16,
DET_LD_DCLK, a data clock based on a programmable bit rate. The bit rate is programmable via variables D1,
D2, and D3 and is always relative to the master clock (XTAL) frequency, F_x. Table 1 shows common bit rates
(kbps) vs selected crystal frequencies (MHz) and the respective settings of D1, D2, and D3.
The preprogrammed bit rate can be calculated based on the following equation:
Bit
rate
(kbps)
+
crystal
D1
frequency (kHz)
D2 D3
+
D1
Fx
D2
D3 ^{+ fc (kHz)}
where:
D1 = 1, 5, 6, or 8
D2 = 1, 2, 4, 8, 16, 32, 64, or 128
D3 = 15 or 16
The data clock circuit is designed to reset/clear internally with no user action required.
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