TPS72501_07 Datasheet, PDF (9/22 Pages) Texas Instruments – LOW INPUT VOLTAGE, 1-A LOW-DROPOUT LINEAR REGULATORS WITH SUPERVISOR

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APPLICATION INFORMATION
TPS72501
TPS72515, TPS72516
TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
The TPS725xx family of low-dropout (LDO) regulators has numerous features that make it applicable to a wide
range of applications. The family operates with very low input voltage (≥1.8 V) and low dropout voltage (typically
200 mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode
power supplies. Both the active low RESET and 1-A output current make the TPS725xx family ideal for powering
processor and FPGA supplies. The TPS725xx family also has low output noise (typically 150 µV_RMS with 10-µF
output capacitor), making it ideal for use in telecom equipment.
External Capacitor Requirements
A 1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS725xx, is required for stability. To improve transient response, noise rejection, and ripple rejection, an
additional 10-µF or larger, low ESR capacitor is recommended. A higher-value, low ESR input capacitor may be
necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the
power source, especially if the minimum input voltage of 1.8 V is used.
Although an output capacitor is not required for stability, transient response and output noise are improved with a
10-µF output capacitor.
Programming the TPS72501 Adjustable LDO Regulator
The output voltage of the TPS72501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 19. The output voltage is calculated using:
ǒ Ǔ VO + Vref
1
)
R1
R2
(1)
Where:
• V_FB = V_REF = 1.22 V typical (see the electrical characteristics for V_REF range)
Resistors R1 and R2 should be chosen for approximately 10-µA divider current. Lower value resistors offer no
inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase
the output voltage error. The recommended design procedure is to choose R2 = 120 kΩ to set the divider current
at 10 µA and then calculate R1 using:
ǒ Ǔ R1 +
VO
Vref
*
1
R2
(2)
V_I
1 µF
≥ 1.3 V
≤ 0.4 V
TPS72501
IN
EN
OUT
R1
1.22 V
FB
GND
R2
V_O
C_o
OUTPUT VOLTAGE
PROGRAMMING GUIDE
(Standard 1% Resistor Values)
PROGRAM
VOLTAGE
1.8 V
2.5 V
3.3 V
3.6 V
ACTUAL
R1 (KΩ) R2 (kΩ) VOLTAGE
56.2
118
1.801
127
121
2.500
196
115
3.299
205
105
3.602
Figure 19. TPS72501 Adjustable LDO Regulator Programming
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