TPS718XX_07 Datasheet, PDF (9/18 Pages) Texas Instruments – Dual, 200mA Output, Low Noise, High PSRR Low-Dropout Linear Regulators in 2mm x 2mm SON Package

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TPS718xx
TPS719xx
SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007
APPLICATION INFORMATION
The TPS718xx/TPS719xx belong to a family of new
generation LDO regulators that use innovative
circuitry to achieve ultra-wide bandwidth and high
loop gain, resulting in extremely high PSRR (up to
1MHz) at very low headroom (V_IN – V_OUT). These
features, combined with low noise, two independent
enables, low ground pin current and ultra-small
packaging, make this part ideal for portable
applications. This family of regulators offer
sub-bandgap output voltages, current limit and
thermal protection, and is fully specified from –40°C
to +125°C.
Figure 22 shows the basic circuit connections.
2.7V - 6.5V
V_IN
1mF
On
Off
On
Off
IN
OUT1
TPS718xx
TPS719xx
EN1
OUT2
EN2
GND
0.9V - 3.6V
1mF
0.9V - 3.6V
1mF
V_OUT
V_OUT
Figure 22. Typical Application Circuit
Input and Output Capacitor Requirements
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1.0µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or if the device is
located close to the power source. If source
impedance is not sufficiently low, a 0.1µF input
capacitor may be necessary to ensure stability.
The TPS718xx/TPS719xx are designed to be stable
with standard ceramic capacitors of values 1.0µF or
larger at the output. X5R- and X7R-type capacitors
are best because they have minimal variation in
value and ESR over temperature. Maximum ESR
should be <1.0Ω.
Board Layout Recommendations to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the board be designed with separate ground
planes for V_IN and V_OUT, with each ground plane
connected only at the GND pin of the device. In
addition, the ground connection for the output
capacitor should connect directly to the GND pin of
the device. High ESR capacitors may degrade
PSRR.
Internal Current Limit
The TPS718xx/TPS719xx internal current limits help
protect the regulator during fault conditions. During
current limit, the output sources a fixed amount of
current that is largely independent of output voltage.
For reliable operation, the device should not be
operated in a current limit state for extended periods
of time.
The PMOS pass element in the
TPS718xx/TPS719xx has a built-in body diode that
conducts current when the voltage at OUT exceeds
the voltage at IN. This current is not limited, so if
extended reverse voltage operation is anticipated,
external limiting to 5% of rated output current may be
appropriate.
Shutdown
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN. The TPS719 with internal active
output pulldown circuitry discharges the output with a
time constant (t) of:
t=3
60 ´ R_L
60 + R_L
´ C_OUT
with:
•
•
R_L = output load resistance
C_OUT = Output capacitance
Dropout Voltage
The TPS718xx/TPS719xx use a PMOS pass
transistor to achieve low dropout. When (V_IN – V_OUT)
is less than the dropout voltage (V_DO), the PMOS
pass device is in its linear region of operation and
the input-to-output resistance is the R_DS(ON) of the
PMOS pass element. V_DO approximately scales with
output current because the PMOS device behaves
like a resistor in dropout.
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