TPS62140_15 Datasheet, PDF (9/40 Pages) Texas Instruments – TPS6214x 3-V to 17-V 2-A Step-Down Converter in 3 × 3 QFN Package

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TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0C – NOVEMBER 2011 – REVISED AUGUST 2015
Feature Description (continued)
Using very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. The TPS6214x
can start into a pre-biased output. During monotonic pre-biased startup, both the power MOSFETs are not
allowed to turn on until the devices internal ramp sets an output voltage above the pre-bias voltage. As long as
the output is below about 0.5 V, a reduced current limit of typically 1.6 A is set internally. If the device is set to
shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin down
to ensure a proper low level. Returning from those states causes a new start-up sequence as set by the SS/TR
connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in
both directions, up and down (see Application and Implementation).
8.3.3 Power Good (PG)
The TPS6214x has a built-in power-good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an
open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic-low level. It is high-impedance when the device is turned off due to EN, UVLO, or
thermal shutdown. TPS62140A features PG=Low in this case and can be used to actively discharge Vout (see
Figure 41). VIN must remain present for the PG pin to stay Low. See SLVA644 for application details.
8.3.4 Pin-Selectable Output Voltage (DEF)
The output voltage of the TPS6214x devices can be increased by 5% above the nominal voltage by setting the
DEF pin to High . When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6214x can be found in SLVA489. A pull down resistor of about
400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating
after initially set to Low. The resistor is disconnected if the pin is set High.
8.3.5 Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF pin (see above).
8.3.6 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents incorrect operation of the device by switching off
both the power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational
for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.
8.3.7 Thermal Shutdown
The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_J exceeds 160°C
(typ.), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes high-impedance. When T_J decreases below the hysteresis amount, the converter resumes normal
operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shutdown temperature.
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