TPS54974 Datasheet, PDF (9/18 Pages) Texas Instruments – DUAL INPUT BUS (2.5V, 3.3V) 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs

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PVIN input connected to a separate power source
from VIN. The primary intended application has VIN
connected to a 3.3-V bus and PVIN connected to a
2.5-V bus. The TPS54974 cannot be damaged by
any sequencing of these voltages. However, the
UVLO (see detailed description section) is referenced
to the VIN input. Some conditions may cause unde-
sirable operation.
If PVIN is absent when the VIN input is high, the
slow-start is released, and the PWM circuit goes to
maximum duty factor. When the PVN input ramps up,
the output of the TPS54974 follows the PVIN input
until enough voltage is present to regulate to the
proper output value.
NOTE:
If the PVIN input is controlled via a fast bus switch, it
results in a hard-start condition and may damage the
load (i.e., whatever is connected to the regulated
output of the TPS54974). If a power-good signal is
not available from the 2.5-V power supply, one can
be generated using a comparator and hold the
SS/ENA pin low until the 2.5-V bus power is good. An
example of this is shown in Figure 11. This circuit can
also be used to prevent the TPS54974 output from
following the PVIN input while the PVIN power supply
is ramping up.
100 kΩ
PVIN
10 kΩ
VBIAS
10 kΩ
27.4 kΩ
VIN
+
-
SS/ENA
1/2 LM293
Figure 11. Undervoltage Lockout Circuit for PVIN
Using Open-Collector or Open-Drain Comparator
PVIN and VIN can be tied together for 3.3-V bus
operation.
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor
and 3 x 22-µF capacitor. The inductor is a low
dc-resistance (0.017 Ω) type, Pulse Engineering
PA0277. The capacitors used are 22-µF, 6.3-V cer-
amic types with X5R dielectric. The feedback loop is
compensated so that the unity gain frequency is
approximately 75 kHz.
MAXIMUM OUTPUT VOLTAGE
The maximum attainable output voltage is limited by
the minimum voltage at the PVIN pin. Nominal
maximum duty cycle is limited to 90% in the
TPS54974, so maximum output voltage is:
TPS54974
SLVS458B – JANUARY 2003 – REVISED FEBRUARY 2005
VO(max) + PVIN(min) 0.9
(2)
Care must be taken while operating when nominal
conditions cause duty cycles near 90%. Load transi-
ents can require momentary increases in duty cycle.
If the required duty cycle exceeds 90%, the output
may fall out of regulation.
PCB LAYOUT
Figure 12 shows a generalized PCB layout guide for
the TPS54974.
The PVIN pins should be connected together on the
printed-circuit board (PCB) and bypassed with a
low-ESR ceramic bypass capacitor. Care should be
taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the
TPS54974 ground pins. The minimum recommended
bypass capacitance is 10 µF ceramic with a X5R or
X7R dielectric and the optimum placement is closest
to the VIN pins and the PGND pins. If the VIN is
connected to a separate source supply, it should be
bypassed with its own capacitor.
The TPS54974 has two internal grounds (analog and
power). Inside the TPS54974, the analog ground ties
to all of the noise-sensitive signals, while the power
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the
performance of the TPS54974, particularly at higher
output currents. Ground noise on an analog ground
plane can also cause problems with some of the
control and bias signals. For these reasons, separate
analog and power ground traces are recommended.
There should be an area of ground on the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes. Use
additional vias at the ground side of the input and
output filter capacitors as well. The AGND and PGND
pins should be tied to the PCB ground by connecting
them to the ground area under the device as shown.
The only components that should tie directly to the
power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling ca-
pacitor, and the PGND pins of the TPS54974. Use a
separate wide trace for the analog ground signal
path. This analog ground should be used for the
voltage set-point divider, timing resistor RT, slow-start
capacitor, and bias-capacitor grounds. Connect this
trace directly to AGND (pin 1).
The PH pins should be tied together and routed to
the output inductor. Because the PH connection is
the switching node, the inductor should be located
close to the PH pins and the area of the PCB
conductor minimized to prevent excessive capacitive
coupling.
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