TPS3606-33 Datasheet, PDF (9/18 Pages) Texas Instruments – BATTERY-BACKUP SUPERVISOR FOR LOW-POWER PROCESSORS

TPS3606Ć33
BATTERYĆBACKUP SUPERVISOR FOR LOWĆPOWER PROCESSORS
SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
Vhys
IIH
IIL
II
IOS
IDD
I(BAT)
Ci
PARAMETER
Hysteresis
High-level input current
Low-level input current
Input current
Short-circuit current
VDD supply current
VBAT supply current
Input capacitance
VIT
VPFI
V(SWN)
WDI
MR
WDI
MR
PFI, MSWITCH
PFO
TEST CONDITIONS
1.65 V < VIT < 2.5 V
2.5 V < VIT < 3.5 V
3.5 V < VIT < 5.5 V
1.65 V < V(SWN) < 2.5 V
2.5 V < V(SWN) < 3.5 V
3.5 V < V(SWN) < 5.5 V
WDI = VDD = 5.5 V
MR = 0.7 × VDD, VDD = 5 V
WDI = 0 V,
VDD = 5 V
MR = 0 V,
VDD = 5 V
VI < VDD
PFO = 0 V,
VDD = 1.8 V
PFO = 0 V,
VDD = 3.3 V
PFO = 0 V,
VDD = 5 V
VOUT = VDD
VOUT = VBAT
VOUT = VDD
VOUT = VBAT
VI = 0 V to 5 V
MIN
−33
−110
−25
−0.1
TYP
20
40
50
12
85
100
110
5
MAX
UNIT
mV
150 µA
−76
−150
−255
25 nA
−0.3
−1.1 mA
−2.4
40
µA
8
0.1
µA
40
pF
timing requirements at R_L = 1 MΩ, C_L = 50 pF, T_A = −40°C to 85°C
PARAMETER
TEST CONDITIONS
VDD VIH = VIT + 0.2 V, VIL = VIT − 0.2 V
tw
Pulse width MR
WDI
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
MIN TYP
5
MAX
UNIT
µs
100
ns
switching characteristics at R_L= 1 MΩ, C_L = 50 pF, T_A = −40°C to 85°C
PARAMETER
TEST CONDITIONS
td
Delay time
VDD ≥ VIT + 0.2 V, MR ≥ 0.7 x VDD,
See timing diagram
t(tout) Watchdog time-out
tPHL
Propagation (delay) time,
high-to-low-level output
Transition time
VDD to RESET
PFI to PFO
MR to RESET
VDD to VBAT
VDD > VIT + 0.2 V, See timing diagram
VIL = VIT − 0.2 V,
VIH = VIT + 0.2 V
VIL = V(PFI) − 0.2 V, VIH = V(PFI) + 0.2 V
VDD ≥ VIT + 0.2 V, VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VIL = V(BAT) − 0.2 V, VIH = V(BAT) + 0.2 V,
V(BAT) < VIT
MIN TYP MAX UNIT
60 100 140 ms
0.48 0.8 1.12 s
2
5 µs
3
5 µs
0.1
1 µs
3 µs
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