TCA6507_10 Datasheet, PDF (9/32 Pages) Texas Instruments – LOW-VOLTAGE 7-BIT I2C AND SMBus LED DRIVER WITH INTENSITY CONTROL AND SHUTDOWN

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TCA6507
LOW-VOLTAGE 7-BIT I²C AND SMBus LED DRIVER
WITH INTENSITY CONTROL AND SHUTDOWN
SCPS164B – MAY 2007 – REVISED NOVEMBER 2007
The Fully-On Time register (register 4) defines the time spent at maximum intensity between the fade-on state
and fade-off state for the LED per region B in Figure 7. The first four bits (C7–C4) in this register set the fully-on
time for BANK1, and the next four bits (C3–C0) set the fully-on time for BANK0. The data for each bank is a
binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the most
significant bit (MSB) is bit C3, while the LSB is bit C0. See Table 13 for more information.
BANK
BIT
DEFAULT
Table 9. Register 4 (Fully-On Time Register)
BANK1
BANK0
C7
C6
C5
C4
C3
C2
C1
C0
0
1
0
0
0
1
0
0
The Fade-Off Time register (register 5) defines the time from the fully-on state to the fully-off state for the LED
per region C in Figure 7. The first four bits (C7–C4) in this register set the fade-off time for BANK1, and the next
four bits (C3–C0) set the fade-off time for BANK0. The data for each bank is a binary number between 0 and 15.
For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the MSB is bit C3, while the least significant
bit (LSB) is bit C0. See Table 13 for more information.
BANK
BIT
DEFAULT
Table 10. Register 5 (Fade-Off Time Register)
BANK1
BANK0
C7
C6
C5
C4
C3
C2
C1
C0
0
1
0
0
0
1
0
0
The first and second Fully-Off Time registers (registers 6 and 7) define the time spent at zero intensity (in the
fully-off state of the LED) per region D and E, respectively, in Figure 7. The first four bits (C7–C4) in this register
set the fully-off time for BANK1, and the next four bits (C3–C0) set the fully-off time for BANK0. The data for
each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For
BANK0, the MSB is bit C3, while the LSB is bit C0. See Table 13 for more information.
BANK
BIT
DEFAULT
Table 11. Register 6 (First Fully-Off Time Register)
BANK1
BANK0
C7
C6
C5
C4
C3
C2
C1
C0
0
1
0
0
0
1
0
0
BANK
BIT
DEFAULT
Table 12. Register 7 (Second Fully-Off Time Register)
BANK1
BANK0
C7
C6
C5
C4
C3
C2
C1
C0
0
1
0
0
0
1
0
0
Copyright © 2007, Texas Instruments Incorporated
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