SN74LVCH16901 Datasheet, PDF (9/11 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

From Output
Under Test
CL = 30 pF
(see Note A)
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES145A – OCTOBER 1998 – REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
V_CC = 2.5 V ± 0.2 V
500 Ω ^S1
500 Ω
2 × VCC
Open
GND
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCC
GND
LOAD CIRCUIT
Timing
Input
Data
Input
VCC/2
tsu
th
VCC/2
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
0V
VCC
0V
Input
VCC/2
VCC/2
VCC
0V
tPLH
Output
VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPHL
VOH
VCC/2
VOL
Input
tw
VCC/2
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
0V
Output
Control
(low-level
enabling)
VCC/2
VCC/2
VCC
0V
tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
tPLZ
VCC
VOL + 0.15 V
VOL
tPZH
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9