PCM1727E2K Datasheet, PDF (9/19 Pages) Texas Instruments – DIGITAL-TO-ANALOG CONVERTER With Programmable Dual PLL

MAPPING OF PROGRAM REGISTERS
MODE0
B15 B14 B13 B12 B11 B10
res
res
res
res
res
A1
MODE1
res
res
res
res
res
A1
MODE2
res
res
res
res
res
A1
MODE3
res
res
res
res
res
A1
B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUT
A0
IZD SF1 SF0 DSR1 DSR0 res ATC LRP I²S
SPECIAL FUNCTIONS
The PCM1727 includes several special functions, including
digital attenuation, digital de-emphasis, soft mute, data for-
mat selection and input word resolution. These functions are
controlled using a three-wire interface. MD (pin 9) is used
for the program data, MC (pin 8) is used to clock in the
program data, and ML (pin 7) is used to latch in the program
data. Table III lists the selectable special functions.
FUNCTION
Input Audio Data Format Selection
Normal Format
I²S Format
Input Audio Data Bit Selection
16/20/24 Bits
Input LRCIN Polarity Selection
Lch/Rch = High/Low
Lch/Rch = Low/High
De-emphasis Control
Soft Mute Control
Attenuation Control
Lch, Rch Individually
Lch, Rch Common
Infinite Zero Detection Circuit Control
Operation Enable (OPE)
Sampling Rate Selection
Standard Sampling Rate—44.1/48kHz
Double Sampling Rate—96kHz
Sampling Frequency
44.1kHz Group
48kHz Group
Analog Output Mode
L, R, Mono, Mute
DEFAULT MODE
Normal Format
16 Bits
Lch/Rch = High/Low
OFF
OFF
0dB
Lch, Rch Individually Fixed
OFF
Enabled
Standard Sampling Rate
44.1kHz
Stereo
TABLE III. Selectable Functions.
PROGRAM REGISTER BIT MAPPING
The PCM1727 special functions are controlled using four
program registers which are 16 bits long. These registers are
all loaded using MD. After the 16 data bits are clocked in,
ML is used to latch in the data to the appropriate register.
Table IV shows the complete mapping of the four registers
and Figure 8 illustrates the serial interface timing.
REGISTER
NAME
Register 0
Register 1
Register 2
Register 3
BIT
NAME
AL (7:0)
LDL
A (1:0)
res
AR (7:0)
LDL
A (1:0)
res
MUT
DEM
OPE
IW (1:0)
PL (3:0)
A (1:0)
res
I²S
LRP
ATC
DSR (1:0)
SF (1:0)
IZD
A (1:0)
res
DESCRIPTION
DAC Attenuation Data for Lch
Attenuation Data Load Control for Lch
Register Address
Reserved, should be “L”
DAC Attenuation Data for Rch
Attenuation Data Load Control for Rch
Register Address
Reserved, should be “L”
Left and Right DACs Soft Mute Control
De-emphasis Control
Left and Right DACs Operation Control
Input Audio Data Bit Select
Output Mode Select
Register Address
Reserved, should be “L”
Audio Data Format Select
Polarity of LRCIN (pin 19) Select
Attenuator Control
Double Sampling Rate Select
Sampling Rate Select
Infinite Zero Detection Circuit Control
Register Address
Reserved, should be “L”
TABLE IV. Internal Register Mapping.
REGISTER 0 (A1 = 0, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
ATT = [20 log10 (ATT_DATA/255)] dB
ATTENUATION DATA LOAD CONTROL
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.
PCM1727
9
SBAS077A
www.ti.com