PCA9548APWRG4 Datasheet, PDF (9/27 Pages) Texas Instruments – 8-CHANNEL I2C SWITCH WITH RESET

www.ti.com
Not Recommended For New Designs
PCA9548A
8-CHANNEL I²C SWITCH
WITH RESET
SCPS143C – OCTOBER 2006 – REVISED JUNE 2007
Slave Address
Control Register
SDA S 1 1 1 0 A2 A1 A0 0 A B7 B6 B5 B4 B3 B2 B1 B0 A P
Start Condition
R/W ACK From Slave
ACK From Slave
Figure 7. Write to Control Register
Stop Condition
Reads
The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 4 for device
address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.
After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the
SCn/SDn channel defined by the command byte then is sent by the PCA9548A (see Figure 8). After a restart,
the value of the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed
when the restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse.
There is no limitation on the number of data bytes received in one read transmission, but when the final byte is
received, the bus master must not acknowledge the data.
Slave Address
Control Register
SDA S 1 1 1 0 A2 A1 A0 1 A B7 B6 B5 B4 B3 B2 B1 B0 NA P
Start Condition
R/W ACK From Slave
NACK From Master Stop Condition
Figure 8. Read From Control Register
Submit Documentation Feedback
9