LM5021MM-2 Datasheet, PDF (9/23 Pages) Texas Instruments – LM5021 AC-DC Current Mode PWM Controller

LM5021
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SNVS359D – MAY 2005 – REVISED MARCH 2013
C_VCC
VIN = 20V - 8.5V x
C_VIN
(3)
Assuming C_VIN value as 10 µF, and C_VCC of 1µF, then the drop in VIN will be 0.85V, or the VIN value drops to
19.15V. The value of the VCC capacitor can be small (less than 1uF) as it supplies only transient gate drive
current of a short duration. The C_VIN capacitor must be sized to supply the gate drive current and the quiescent
current of LM5021until the transformer bias winding delivers sufficient voltage to VIN to sustain the VCC voltage.
The C_VIN capacitor value can be calculated from the operating VCC load current after it's output voltage reaches
the VCC UVLO threshold. For example, if the LM5021 is driving an external MOSFET with total gate charge (Qg)
of 25nC, the average gate drive current is Qg x Fsw, where Fsw is the switching frequency. Assuming a
switching frequency of 150KHz, the average gate drive current is 3.75mA. Since the IC consumes approximately
2.5mA operating current in addition to the gate current, the total current drawn from C_VIN capacitor is the
operating current plus the gate charge current, or 6.25mA. The C_VIN capacitor must supply this current for a brief
time until the transformer bias winding takes over. The C_VIN voltage must not fall below 8.5V during the start-up
sequence or the cycle will be restarted. The maximum allowable start-up time can be calculated using the value
of C_VIN, the change in voltage allow at VIN (19.15V – 8.5V) and the VCC regulator current (6.25mA). Tmax, the
maximum time allowed to energize the bias winding is:
C_VIN x (19.15V - 8.5V)
Tmax =
= 17 ms
6.25 mA
(4)
If the calculated value of Tmax is too small, the value of Cin should be increased further to allow more time
before the transformer bias winding takes over and delivers the operating current to the VCC regulator.
Increasing C_VIN will increase the time from the application of the rectified ac (HV in the Figure 9) to the time when
VIN reaches the 20V start threshold. The initial charging time of C_VIN is:
20V ^-1
T_{VIN_THRESHOLD} = R_START x C_VIN x ln
1-
HV
(5)
PWM COMPARATOR/SLOPE COMPENSATION
The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The
COMP pin voltage is reduced by 1.25V then attenuated by a 3:1 resistor divider. The PWM comparator input
offset voltage is designed such that less than 1.25V at the COMP pin will result in a zero duty cycle at the
controller output.
For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By
adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this
oscillation can be avoided. The LM5021-1 integrates this slope compensation by summing a ramp signal
generated by the oscillator with the current sense signal. The slope compensation is generated by a current ramp
driven through an internal 1.8 kΩ resistor connected to the CS pin. Additional slope compensation may be added
by increasing the resistance between the current sense filter capacitor and the CS pin, thereby increasing the
voltage ramp created by the oscillator current ramp. Since the LM5021-2 is not capable of duty cycles greater
than 50%, there is no slope compensation feature in this device.
CURRENT LIMIT/CURRENT SENSE
The LM5021 provides a cycle-by-cycle over current protection feature. Current limit is triggered by an internal
current sense comparator threshold which is set at 500mV. If the CS pin voltage plus the slope compensation
voltage exceeds 500mV, the OUT pin output pulse will be immediately terminated.
An RC filter, located near the LM5021, is recommended for the CS pin to attenuate the noise coupled from the
power FET's gate to source. The CS pin capacitance is discharged at the end of each PWM clock cycle by an
internal switch. The discharge switch remains on for an additional 90ns leading edge blanking interval to
attenuate the current sense transient that occurs when the external power FET is turned on. In addition to
providing leading edge blanking, this circuit also improves dynamic performance by discharging the current
sense filter capacitor at the conclusion of every cycle.
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