LM2747_15 Datasheet, PDF (9/38 Pages) Texas Instruments – Synchronous Buck Controller with Pre-Bias Startup, and Optional Clock Synchronization

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FREQ/SYNC
BLOCK DIAGRAM
SD
V_CC
LM2747
SNVS370B – MARCH 2006 – REVISED MARCH 2013
PGND
SGND
PGND
PWGD
SS/TRACK
CLOCK &
PLL
RAMP
10 Ps
DELAY
SSDONE
SHUT DOWN
LOGIC
10 PA
OV
0.71V
UV
0.434V
90 PA
Soft-Start
Comparator
+ Logic
REF
V_REF=0.6V
1V_PP
+
EA
-
UVLO
SYNCHRONOUS
DRIVER LOGIC
PWM
PWM LOGIC
Zero Detector
40 PA
-
ILIM
+
BOOT
HG
LG
I_SEN
FB
EAO
Figure 17. Block Diagram
APPLICATION INFORMATION
The LM2747 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has output shutdown (SD), input undervoltage lock-out (UVLO) mode and power
good (PWGD) flag (based on overvoltage and undervoltage detection). The overvoltage and undervoltage
signals are OR-gated to drive the power good signal and provide a logic signal to the system if the output voltage
goes out of regulation. Current limit is achieved by sensing the voltage V_DS across the low side MOSFET. The
LM2747 is also able to start-up with the output pre-biased with a load and allows for the switching frequency to
be synchronized with an external clock source.
START UP/SOFT-START
When V_CC exceeds 2.79V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor C_SS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2747 reference voltage of 0.6V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance of C_SS determines the
length of the soft-start period, and can be approximated by:
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