DS92LV1212A Datasheet, PDF (9/17 Pages) National Semiconductor (TI) – 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

AC Timing Diagrams and Test Circuits (Continued)
Timing shown for RCLK_R/F = LOW
Duty Cycle (t_RDC) =
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FIGURE 5. Deserializer Setup and Hold Times
FIGURE 6. Deserializer TRI-STATE Test Circuit and Timing
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