DS50PCI402SQ Datasheet, PDF (9/38 Pages) Texas Instruments – DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
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PRSNT#
0
0
0
0
1
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 8. Receiver Detect Pins for A and B ports (LVCMOS inputs)
ENRXDET RXDETA/B
0
0
Input
Termination
>50KΩ to VDD
50Ω
0
1
>50KΩ to VDD
50Ω
1
0
>50KΩ to VDD
1
1
50Ω
X
X
>50KΩ to VDD
Termination sensed on
Output
Hi - Z
PCIe Input
Hi - Z
PCIe Input
X
X
X
Function
Automatic RXDET: Rx detection state machine
enabled. Outputs will test for the presence of a
receiver input every 12 msec until detection
occurs. Input termination remains >50KΩ to
VDD until receiver is detected. Once receiver is
detected, input impedance to VDD is 50Ω.
Automatic RXDET: Rx detection state machine
enabled. Outputs will test for the presence of a
receiver input every 12 msec for 600 msec and
then stop. Input termination remains >50KΩ to
VDD until receiver is detected. Once receiver is
detected, input impedance to VDD is 50Ω.
Restart detection if RXDETA/B is pulsed low-
high.
Manual RXDET: Rx detection state machine
disabled. Input termination >50KΩ. Associated
output channels in low power idle mode.
Manual RXDET: Rx detection state machine
disabled. Input termination 50Ω. Associated
output channels set to active.
Power down mode: Input termination >50KΩ.
Associated output channels off. Part in power
saving mode. PRSNT# should be held high for
a minimum of 5 us to ensure complete analog
power down. The Automatic RXDET
functionality will be re-initialized on the falling
edge of PRSNT#.
RX Detect: Range of Operation
The Rx detection process used in the DS50PCI402 is designed to be fully compliant with the PCIe 2.0 base
specification. The receiver detection circuitry will accurately detect a receiver when both conditions listed below
are true:
• DS50PCI402 within Recommended Operating Range for Temperature and Supply Voltage
• For receiver Z_RX-DC = 40 (min) to 60 (max) Ohms
Note: To ensure robust system operation, the DS50PCI402 will only signal a valid receiver detection if both
halves of the differential output pair detect a proper 40 - 60 Ohm receiver impedance. If the receiver detection
circuitry senses a load impedance greater than Z_RX-DC on either trace of a differential pair, it will be interpreted as
no termination load present (i.e. the corresponding DS50PCI402 input termination will remain High-Z).
Manual Control Of RXDETA/B In A PCIe Environment
In some cases manual control of RXDETA/B may be desirable. In order for upstream and downstream PCIe
subsystems to communicate in a cabling environment, the PCIe specification includes several auxiliary or
sideband signals to manage system-level functionality or implementation. Similar methods are used in backplane
applications, but the exact implementation falls outside the PCIe standard. Initial communication from the
downstream subsystem to the upstream subsystem is done with the CPRSNT# auxiliary signal. The CPRSNT#
signal is asserted Low by the downstream componentry after the "Power Good" condition has been established.
This mechanism allows for the upstream subsystem to determine whether the power is good within the
downstream subsystem, enable the reference clock, and initiate the Link Training Sequence.
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