DAC5675 Datasheet, PDF (9/28 Pages) Texas Instruments – 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER

DAC5675
SLAS352B – DECEMBER 2001 – REVISED JUNE 2002
clock input and timing (continued)
Figure 7 shows the equivalent schematic of the differential clock input buffer. The input nodes are internally
self-biased enabling ac coupling of the clock inputs. Figure 8 shows the preferred configuration for driving the
DAC5675.
TTL/CMOS Source
Ropt
22 Ω
DAC5675
CLK
0.01 µF
CLKC
Node CLKC
Internally Biased
Figure 7. Driving the DAC5675 With a Single-Ended TTL/CMOS Clock Source
Differential ⁺
ECL
or
(LV)PECL
Source _–
RT
50 Ω
RT
50 Ω
CAC
0.01 µF
CAC
0.01 µF
DAC5675
CLK
CLKC
VTT
Figure 8. Driving the DAC5675 With a Differential ECL/PECL Clock Source
Single-Ended
ECL
or
(LV)PECL
Source
ECL/PECL
Gate
RT
50 Ω
RT
50 Ω
CAC
0.01 µF
CAC
0.01 µF
DAC5675
CLK
CLKC
VTT
Figure 9. Driving the DAC5675 With a Single-Ended ECL/PECL Clock Source
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