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CD74HC652 Datasheet, PDF (9/12 Pages) Texas Instruments – High-Speed CMOS Logic Octal-Bus Transceiver/Registers, Three-State
◁
CD74HC652, CD74HCT652
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Three-State Disabling Time Bus tPLZ, tPHZ CL = 50pF
2
-
- 175
-
220
-
265
ns
to Output or Register to Output
4.5 -
-
35
-
44
-
53
ns
6
-
- 30
-
37
-
45
ns
CL = 15pF
5
- 14 -
-
-
-
-
ns
Three-State Enabling Time Bus tPZL, tPZH CL = 50pF
2
-
- 175
-
220
-
265
ns
to Output or Register to Output
4.5 -
-
35
-
44
-
53
ns
6
-
- 30
-
37
-
45
ns
Output Transition Time
CL = 15pF
5
- 14 -
-
-
-
-
ns
tTLH, tTHL CL = 50pF
2
-
- 60
-
75
-
90
ns
4.5 -
-
12
-
15
-
18
ns
6
-
- 10
-
13
-
15
ns
Three-State Output
Capacitance
CO
-
-
-
-
20
-
20
-
20
pF
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
Maximum Frequency
fMAX
CL = 15pF
5
- 60 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 7, 8)
CPD
-
5
- 52 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
Store A Data to B Bus
Store B Data to A Bus
tPLH, tPHL CL = 50pF 4.5 -
-
44
-
55
-
66
ns
CL = 15pF
5
- 18 -
-
-
-
-
ns
Propagation Delay,
A Data to B Bus
B Data to A Bus
tPLH, tPHL CL = 50pF 4.5 -
-
37
-
46
-
56
ns
CL = 15pF
5
- 15 -
-
-
-
-
ns
Propagation Delay,
Select to Data
tPLH, tPHL CL = 50pF 4.5 -
-
46
-
58
-
69
ns
CL = 15pF
5
- 19 -
-
-
-
-
ns
Three-State Disabling Time Bus tPLZ, tPHZ CL = 50pF 4.5 -
-
35
-
44
-
53
ns
to Output or Register to Output
CL = 15pF
5
- 14 -
-
-
-
-
ns
Three-State Enabling Time Bus tPZL, tPZH CL = 50pF 4.5 -
-
45
-
56
-
68
ns
to Output or Register to Output
CL = 15pF
5
- 19 -
-
-
-
-
ns
Output Transition Time
tTLH, tTHL CL = 50pF 4.5 -
-
12
-
15
-
18
ns
Three-State Output
Capacitance
CO
-
-
-
-
20
-
20
-
20
pF
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
Maximum Frequency
fMAX
CL = 15pF
5
- 45 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 7, 8)
CPD
-
5
- 52 -
-
-
-
-
pF
NOTES:
7. CPD is used to determine the dynamic power consumption, per package.
8. PD = VCC2 CPD fi + Σ VCC2 CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch capaci-
tance, VCC = supply voltage.
9
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