CD54HC40105 Datasheet, PDF (9/19 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
V_CC
SYMBOL CONDITIONS (V)
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
Three-State Output
Capacitance
C_O C_L = 50pF
-
-
-
15
-
15
-
15
pF
HCT TYPES
Propagation Delay Time
MR to DIR, DOR
SI to DIR
SO to DOR
SO to Qn
Propagation Delay/Ripple thru
Delay
SI to DOR
t_PLH,
t_PHL
t_PLH,
t_PHL
t_PLH,
t_PHL
t_PLH,
t_PHL
t_PLH
C_L = 50pF
C_L = 15pF
C_L = 50pF
C_L =15pF
C_L = 50pF
C_L =15pF
C_L = 50pF
C_L =15pF
C_L = 50pF
4.5
-
-
36
-
45
-
54
ns
5
-
15
-
-
-
-
-
ns
4.5
-
-
42
-
53
-
63
ns
5
-
18
-
-
-
-
-
ns
4.5
-
-
42
-
53
-
63
ns
5
-
18
-
-
-
-
-
ns
4.5
-
-
80
-
100
-
120
ns
5
-
35
-
-
-
-
-
ns
4.5
-
- 400
-
500
-
600
ns
Propagation Delay/Ripple thru
Delay
SO to DIR
t_PLH C_L = 50pF
4.5
-
- 500
-
625
-
750
ns
Propagation Delay/Ripple thru
Delay
SI to Qn
t_PLH C_L = 50pF
4.5
-
- 300
-
380
-
450
ns
Three-State Output Enable
OE to Q_n
Three-State Output Disable
OE to Qn
t_PZH, t_PZL C_L = 50pF
t_PHZ, t_PLZ C_L = 50pF
4.5
-
-
35
-
44
-
53
ns
4.5
-
-
30
-
38
-
45
ns
Output Transition Time
t_TLH, t_THL C_L = 50pF
Maximum CP Frequency
f_MAX C_L =15pF
Input Capacitance
C_IN C_L = 50pF
Power Dissipation Capacitance C_PD C_L =15pF
(Notes 3, 4)
4.5
-
-
15
-
19
-
22
ns
5
-
32
-
-
-
-
-
MHz
-
-
-
10
-
10
-
10
pF
5
-
83
-
-
-
-
-
pF
Three-State Output
Capacitance
C_O C_L = 50pF
-
-
-
15
-
15
-
15
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per package.
4. P_D = C_PD V_CC2 f_i + Σ (C_L V_CC2 f_o) where f_i = Input Frequency, f_o = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply
Voltage.
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