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CD54HC354_07 Datasheet, PDF (9/15 Pages) Texas Instruments – 8-Line to 1-Line Data Selector/Multiplexer/Register With 3-State Outputs
CD54HC354, CD74HC354, CD74HCT354
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
Propagation Delay,
Sn → Y, Y
Propagation Delay,
LE → Y, Y
Output Disabling Time,
OEn to Y, Y
Output Disabling Time,
OE3 to Y, Y
Output Enabling Time,
OEn to Y, Y
Output Enabling Time,
OE3 to Y, Y
Output Transition Time
Input Capacitance
Three-State Capacitance
Power Dissipation
Capacitance
(Notes 4, 5)
SYMBOL
tPLH, tPHL
tPLH, tPHL
tPLZ, tPHZ
tPLZ, tPHZ
tPZL, tPZH
tPZL, tPZH
tTLH, tTHL
CIN
CO
CPD
TEST
CONDITIONS
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
-
-
-
VCC (V)
4.5
5
4.5
5
4.5
5
4.5
5
4.5
5
4.5
5
4.5
-
-
5
25oC
TYP MAX
-
59
25
-
-
63
25
-
-
33
13, 16
-
-
39
13, 16
-
-
34
14
-
-
34
14
-
-
12
-
10
-
20
92
-
-40oC TO 85oC
MAX
74
-
79
-
41
-
49
-
43
-
43
-
15
10
20
-
NOTES:
4. CPD is used to determine the dynamic power consumption, per device.
5. PD = VCC2 (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
-55oC TO
125oC
MAX
89
-
94
-
50
-
59
-
51
-
51
-
18
10
20
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
9