CD54HC192 Datasheet, PDF (9/16 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

CD54/74HC192, CD54/74HC193, CD54/74HCT193
Test Circuits and Waveforms (Continued)
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
P0
P1
PRESET DATA
P2
SEQUENCES:
P3
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BINARY THIRTEEN. CLOCK UP
3. COUNT UP TO FOURTEEN,
FIFTEEN, TERMINAL COUNT UP,
CLOCK DOWN
ZERO, ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
Q₀
TERMINAL COUNT DOWN,
FIFTEEN, FOURTEEN AND
THIRTEEN.
Q₁
OUTPUTS
Q₂
Q₃
TERMINAL COUNT UP
TERMINAL COUNT DOWN
NOTES:
0
13
14 15 0 1 2
1. Master reset overrides load data and clock inputs. RESET PRESET
COUNT UP
2. When counting up, clock-down input must be high.
When counting down, clock-up input must be high.
1 0 15 14 13
COUNT DOWN
FIGURE 2. ’HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
CPU OR CPD
Q_n
l/f_MAX
V_S
V_S
t_W
t_PHL
V_S
INPUT LEVEL
V_S
t_PLH
V_S
FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH
CPU OR CPD
TCU OR TCD
V_S
t_PHL
V_S
INPUT LEVEL
V_S
t_PLH
V_S
FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS
Pn
PL
CPU OR CPD
Q_n
t_W
V_S
V_S
t_PLH
V_S
INPUT LEVEL
t_W
V_S
INPUT LEVEL
V_S
t_PHL
t_REC
V_S
V_S
INPUT LEVEL
FIGURE 5. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
MR
CPU OR CPD
Q_n
V_S
V_S
t_W
t_PHL
V_S
INPUT LEVEL
t_REC
V_S
INPUT LEVEL
FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
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