CC2544_15 Datasheet, PDF (9/29 Pages) Texas Instruments – System-on-Chip for 2.4-GHz USB Applications

CC2544
www.ti.com
SWRS103D – JUNE 2011 – REVISED MAY 2012
DC CHARACTERISTICS
Measured on Texas Instruments CC2544EM reference design with T_A = 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Logic-0 input voltage
0.5
V
Logic-1 input voltage
2.5
V
Logic-0 input current
–50
50
nA
Logic-1 input current
–50
50
nA
I/O pin pullup and pulldown resistors
20
kΩ
Logic-0 output voltage 4-mA pins Output load 4 mA
0.5
V
Logic-1 output voltage 4-mA pins Output load 4 mA
2.4
V
Logic-0 output voltage 20-mA pins Output load 20 mA
0.5
V
Logic-1 output voltage, 20-A pins Outpu load 20 mA
2.4
V
CONTROL INPUT AC CHARACTERISTICS
T_A = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
System clock, f_SYSCLK
t_SYSCLK = 1/ f_SYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
RESET_N low duration
See item 1, Figure 1. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
Interrupt pulse duration
See item 2, Figure 1.This is the shortest pulse that is recognized as
an interrupt request.
MIN TYP
16
MAX UNIT
32 MHz
1
µs
20
ns
RESET_N
Px.n
1
2
Figure 1. Control Input AC Characteristics
T0299-01
SPI AC CHARACTERISTICS
T_A = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
t₁
SCK period
Master, RX and TX
Slave, RX and TX
SCK duty cycle
Master
t₂
SSN low to SCK,
Figure 2 and Figure 3
Master
Slave
t₃
SCK to SSN high
Master
Slave
t₄
MOSI early out
t₅
MOSI late out
t₆
MISO setup
t₇
MISO hold
Master, load = 10 pF
Master, load = 10 pF
Master
Master
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): CC2544
MIN
TYP MAX UNIT
250
ns
250
50%
63
ns
63
63
ns
63
7 ns
10 ns
90
ns
10
ns
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