ADS8513 Datasheet, PDF (9/24 Pages) Texas Instruments – 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE

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CONV
EXT/INT
REF
CDAC
Converter Core
ADS8513
SLAS486 – JUNE 2007
Clock
Control Logic
Each flip-flop in the
working register is
latched as the
conversion proceeds
Working Register
DQ
W0
DQ
DQ
DQ
DQ
•••
W1
W2
W14
Update of the shift
register occurs just prior
to BUSY Rising⁽¹⁾
DQ
DQ
DQ
DQ
W15
Shift Register
DQ
DQ
S0
S1
S2
S14
S15
SOUT
Delay
BUSY
DATA
DATACLK
CS
NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW du ring
this time, the shift register will not be updated and the conversion result will be lost.
Figure 4. Block Diagram of the ADS8513 Digital Inputs and Outputs
CONV
BUSY
t₂₅
t₆ – t₂₅
NOTE: Update of the internal shift register occurs in the
shaded region. If EXT/INT is HIGH, then DATACLK
must be LOW or CS must be HIGH during this time.
Figure 5. Timing of the Shift Register Update
READING DATA
The ADS8513 digital output is in Binary Two’s Complement (BTC) format. Table 3 shows the relationship
between the digital output word and the analog input voltage under ideal conditions.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS8513
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