ADS8330 Datasheet, PDF (9/50 Pages) Texas Instruments – LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS8329
ADS8330
www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 2.7 V, +VBD = 1.8 V (unless otherwise noted) ⁽¹⁾⁽²⁾
f_CCLK
t_su(CSF-EOC)
t_h(CSF-EOC)
t_wL(CONVST)
t_su(CSF-EOS)
t_h(CSF-EOS)
t_su(CSR-EOS)
t_h(CSR-EOS)
t_{su(CSF-SCLK1F)}
t_wL(SCLK)
t_wH(SCLK)
t_c(SCLK)
t_{d(SCLKF-SDOINVALID)}
t_{d(SCLKF-SDOVALID)}
t_{d(CSF-SDOVALID)}
t_{su(SDI-SCLKF)}
t_h(SDI-SCLKF)
t_d(CSR-SDOZ)
t_{su(16th SCLKF-CSR)}
t_d(SDO-CDI)
PARAMETER
Frequency, conversion clock, CCLK
Setup time, falling edge of CS to EOC
Hold time, falling edge of CS to EOC
Pulse duration, CONVST low
Setup time, falling edge of CS to EOS
Hold time, falling edge of CS to EOS
Setup time, rising edge of CS to EOS
Hold time, rising edge of CS to EOS
Setup time, falling edge of CS to first
falling SCLK
Pulse duration, SCLK low
Pulse duration, SCLK high
Cycle time, SCLK
Delay time, falling edge of SCLK to SDO
invalid
Delay time, falling edge of SCLK to SDO
valid
Delay time, falling edge of CS to SDO
valid, SDO MSB output
Setup time, SDI to falling edge of SCLK
Hold time, SDI to falling edge of SCLK
Delay time, rising edge of CS/FS to SDO
3-state
Setup time, 16th falling edge of SCLK
before rising edge of CS/FS
Delay time, CDI high to SDO high in
daisy chain mode
External, 3 V ≤ +VA ≤ 3.6 V,
f_CCLK = 1/2 f_SCLK
External, 2.7 V ≤ +VA ≤ 3 V,
f_CCLK = 1/2 f_SCLK
Internal,
f_CCLK = 1/2 f_SCLK
All modes,
3 V ≤ +VA ≤ 3.6 V
All modes,
2.7 V ≤ +VA < 3 V
10-pF Load
10-pF Load
10-pF Load,
2.7 V ≤ +VA ≤ 3 V
10-pF Load,
3 V ≤ +VA ≤ 3.6 V
10-pF Load, chain mode
MIN
0.5
0.5
20
1
0
40
20
20
20
20
5
8
8
23.8
26.5
7.5
8
4
10
TYP
MAX UNIT
21
18.9 MHz
22.3
23.5
CCLK
ns
ns
ns
ns
ns
ns
ns
t_c(SCLK) – 8 ns
t_c(SCLK) – 8 ns
2000
ns
2000
ns
16 ns
13
ns
11
ns
ns
8 ns
ns
23 ns
(1) All input signals are specified with t_r = t_f = 1.5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) See timing diagrams.
Copyright © 2006–2009, Texas Instruments Incorporated
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