ADS8324 Datasheet, PDF (9/14 Pages) Texas Instruments – 14-Bit, High Speed, 1.8V MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER

DIGITAL INTERFACE
SIGNAL LEVELS
The CMOS digital output (D_OUT) will swing from 0V to
V_CC. If V_CC is 3V, and this output is connected to a 5V
CMOS logic input, then that IC may require more supply
current than normal and may have a slightly longer propaga-
tion delay.
SERIAL INTERFACE
The ADS8324 communicates with microprocessors and
other digital systems via a synchronous 3-wire serial inter-
face, as shown in Figure 5 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for D_OUT is acceptable,
the system can use the falling edge of DCLOCK to
capture each bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D_OUT is enabled and will output a LOW
value for one clock period. For the next 16 DCLOCK
periods, D_OUT will output the conversion result, most sig-
nificant bit first followed by two zeros on clock cycles 15
and 16. After the two zero “dummy bits” have been output,
subsequent clocks will repeat the output data but in a least
significant bit first format starting with a zero.
CS must be taken HIGH following a conversion in order to
place DOUT in tri-state. Subsequent clocks will have no
effect on the converter. A new conversion is initiated only
when CS has been taken HIGH and returned LOW.
SYMBOL
DESCRIPTION
MIN
t_SMPL
t_CONV
t_CYC
t_CSD
Analog Input Sample Time 4.5
Conversion Time
Throughput Rate
CS Falling to
DCLOCK LOW
t_SUCS
CS Falling to
50
DCLOCK Rising
t_hDO
DCLOCK Falling to
5
Current D_OUT Not Valid
t_dDO
DCLOCK Falling to Next
D_OUT Valid
t_dis
CS Rising to D_OUT Tri-State
t_en
DCLOCK Falling to D_OUT
Enabled
t_f
D_OUT Fall Time
t_r
D_OUT Rise Time
TYP MAX UNITS
5.0 Clk Cycles
16
Clk Cycles
50
kHz
0
ns
ns
20
ns
100 250
ns
50 100
ns
100 200
ns
50 150
ns
75 200
ns
TABLE I. Timing Specifications (V_CC = 1.8V) –40°C to
+85°C.
See Figure 6 for test conditions.
DATA FORMAT
The output data from the ADS8324 is in Binary Two’s
Complement format, as shown in Table II. This table repre-
sents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
DESCRIPTION
Full-Scale Range
Least Significant
Bit (LSB)
+Full Scale
Midscale
Midscale – 1LSB
–Full Scale
ANALOG VALUE
2 • V_REF
2 • V_REF/16384
+V_REF – 1 LSB
0V
0V – 1 LSB
–V_REF
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
BINARY CODE
0111 1111 1111 1100
0000 0000 0000 0000
1111 1111 1111 1100
1000 0000 0000 0000
HEX CODE
7FFC
0000
FFFC
8000
TABLE II. Ideal Input Voltages and Output Codes.
CS/SHDN
DCLOCK
D_OUT
t_SUCS
Sample
Complete Cycle
Conversion
Power Down
t_CSD
Use positive clock edge for data transfer
Hi-Z
Hi-Z
0 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0
t_SMPL
(MSB)
t_CONV
(LSB)
NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
FIGURE 5. ADS8324 Basic Timing Diagrams.
ADS8324
9
SBAS172A
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