ADS5204 Datasheet, PDF (9/20 Pages) Texas Instruments – DUAL 10 BIT 40MSPS LOW POWER ANALOG TO DIGITAL CONVERTER WITH PGA

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TIMING DIAGRAMS (Cont.)
SCLK
CS
SDI
t _WH(CS)
1
2
t_{SU(CS_CK)}
t_SU(D)
t _H(D)
D15
D14
t_WH t_WL
3
4
D13
D12
Figure 5. Serial Data Write.
ADS5204
SBAS268A – JUNE 2002 – REVISED JULY 2002
15
16
t _{SU(C16_CS)}
D01
D00
Table 1. Register Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PGA4 PGA3 PGA2 PGA1 PGA0 PGA4 PGA3 PGA2 PGA1 PGA0
0
0 Reserved TWOS MODE SELB
B
B
B
B
B
A
A
A
A
A
Always write 0
Default (power-up) condition for this register is all bits = 0.
The user register is updated on either the first rising edge
of SCLK after the 16th falling edge or CS rising, whichever
comes first. Raising CS before 16 falling SCLK edges
have been seen is an incomplete write error and no
register update will occur. The PGA gain settings are
resynchronized to the internal data conversion clock to
avoid data glitches caused by changing gain settings
while sampling the inputs.
PGA gain control data is applied to the PGAs on the
second falling edge of the ADC sample clock
(CLK40INT) after a successful register write. This
resynchronization ensures that no analog glitch occurs
even when SCLK is asynchronous to CLK.
Note that only the PGA data is resynchronized. The
TWOS, MODE, and SELB register bits take effect
immediately after a successful register write.
OUTPUT DATA FORMAT
The output data format can either be in Binary Two’s
Complement ouput mode or in unsigned binary mode,
which affects both A and B channels.
TWOS – Binary Two’s Complement Mode:
0 – Unsigned Binary
1 – Binary Two’s Complement Output.
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