SMV320C6727B-SP_15 Datasheet, PDF (88/112 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SMV320C6727B-SP
SPRS675G – FEBRUARY 2013 – REVISED JANUARY 2014
www.ti.com
Table 4-34. Additional⁽¹⁾ SPI Slave Timings, 5-Pin Option⁽²⁾⁽³⁾
NO.
25
t_{d(SCSL_SPC)S}
26
t_{d(SPC_SCSH)S}
27
t_{ena(SCSL_SOMI)S}
28
t_{dis(SCSH_SOMI)S}
29
t_{ena(SCSL_ENA)S}
30
t_{dis(SPC_ENA)S}
PARAMETER
Required delay from SPIx_SCS asserted at slave to first
SPIx_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Required delay from final
SPIx_CLK edge before
SPIx_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Delay from master asserting SPIx_SCS to slave driving
SPIx_SOMI valid
Delay from master deasserting SPIx_SCS to slave 3-stating
SPIx_SOMI
Delay from master deasserting SPIx_SCS to slave driving
SPIx_ENA valid
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Delay from final clock
receive edge on SPIx_CLK
to slave 3-stating or driving
high SPIx_ENA.⁽⁴⁾
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
MIN
P
0.5t_c(SPC)M + P + 10
P + 10
0.5t_c(SPC)M + P + 10
P + 10
TYP
MAX UNIT
ns
ns
P + 15 ns
P + 15 ns
15 ns
2P + 15
2P + 15
ns
2P + 15
2P + 15
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-28).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPIx_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
88
Peripheral and Electrical Specifications
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