TLV320DAC3100-Q1_15 Datasheet, PDF (83/101 Pages) Texas Instruments – Low-Power Stereo Audio DAC With Audio Processing and Mono Class-D Speaker Amplifier

TLV320DAC3100-Q1
www.ti.com
SLAS896A – JULY 2013 – REVISED AUGUST 2013
BIT
D7–D3
D2
READ/
WRITE
R/W
R/W
D1
R
D0
R/W
RESET
VALUE
0000 0
0
0
0
Page 8 / Register 1 (0x01): DAC Coefficient RAM Control
DESCRIPTION
Reserved. Write only the reset value.
DAC Adaptive Filtering Control
0: Adaptive filtering disabled in DAC processing block
1: Adaptive filtering enabled in DAC processing block
DAC Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, DAC processing block accesses DAC coefficient buffer A, and the external
control interface accesses DAC coefficient buffer B.
1: In adaptive filter mode, DAC processing block accesses DAC coefficient buffer B, and the external
control interface accesses DAC coefficient buffer A.
DAC Adaptive Filter Buffer Switch Control
0: DAC coefficient buffers are not switched at the next frame boundary.
1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled.
This bit self-clears on switching.
The remaining page-8 registers are either reserved registers or are used for setting coefficients for the
various filters in the TLV320DAC3100-Q1 Reserved registers should not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is
interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When
programming any coefficient value for a filter, the MSB register should always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both
registers should be written in this sequence. Table 6-2 is a list of the page-8 registers, excepting the
previously described register 0 and register 1.
REGISTER
NUMBER
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
23 (0x17)
24 (0x18)
RESET VALUE
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
Table 6-2. Page 8 DAC Buffer A Registers
REGISTER NAME
Coefficient N0(15:8) for left DAC-programmable biquad A
Coefficient N0(7:0) for left DAC-programmable biquad A
Coefficient N1(15:8) for left DAC-programmable biquad A
Coefficient N1(7:0) for left DAC-programmable biquad A
Coefficient N2(15:8) for left DAC-programmable biquad A
Coefficient N2(7:0) for left DAC-programmable biquad A
Coefficient D1(15:8) for left DAC-programmable biquad A
Coefficient D1(7:0) for left DAC-programmable biquad A
Coefficient D2(15:8) for left DAC-programmable biquad A
Coefficient D2(7:0) for left DAC-programmable biquad A
Coefficient N0(15:8) for left DAC-programmable biquad B
Coefficient N0(7:0) for left DAC-programmable biquad B
Coefficient N1(15:8) for left DAC-programmable biquad B
Coefficient N1(7:0) for left DAC-programmable biquad B
Coefficient N2(15:8) for left DAC-programmable biquad B
Coefficient N2(7:0) for left DAC-programmable biquad B
Coefficient D1(15:8) for left DAC-programmable biquad B
Coefficient D1(7:0) for left DAC-programmable biquad B
Coefficient D2(15:8) for left DAC-programmable biquad B
Coefficient D2(7:0) for left DAC-programmable biquad B
Coefficient N0(15:8) for left DAC-programmable biquad C
Coefficient N0(7:0) for left DAC-programmable biquad C
Coefficient N1(15:8) for left DAC-programmable biquad C
Copyright © 2013, Texas Instruments Incorporated
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