TVP3020 Datasheet, PDF (82/98 Pages) Texas Instruments – Video Interface Palette

Table D – 4. 24-Bit Direct Color (64-Bit Pixel Bus, 2:1) Self-Clocked, Overlay PSEL Switched
REGISTER
INDEX SETTING
(HEX) (HEX)
DESCRIPTION
Input Clock Selection
1A
xx
Any clock can be chosen
Output Clock Selection
1B
49
RCLK = SCLK = /2, VCLK = /2 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
0C
Self clocked, PSEL enabled, overlay when PSEL = 1
Color-Key Control
38
00
Disabled – pointing to nonpalette graphics
Multiplexer-Control Register 1 18
06
24-bit direct color
Multiplexer-Control Register 2 19
1C
24-bit direct color, 64-bit pixel bus width
Table D – 5. 24-Bit Direct Color (64-Bit Pixel Bus, 2:1) Self-Clocked,
Overlay Auxiliary Window Switched
REGISTER
INDEX SETTING
(HEX) (HEX)
DESCRIPTION
Input Clock Selection
1A
xx
Any clock can be chosen
Output Clock Selection
1B
49
RCLK = SCLK = /2, VCLK = /2 (VCLK could be different)
General Control
1D
20
Default settings
Auxiliary Control
29
0A
Self clocked, auxiliary window enabled, overlay in window
Color-Key Control
38
00
Disabled – pointing to nonpalette graphics
Multiplexer-Control Register 1 18
06
24-bit direct color
Multiplexer-Control Register 2 19
1C
24-bit direct color, 64-bit pixel bus width
NOTE: For this mode, the auxiliary-window start and stop registers (Index 10 – 17) must be programmed with the
appropriate window coordinates (within active display). See sections 2.16.5 and 2.16.6.
D–2