TMS320VC5471 Datasheet, PDF (81/97 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
6.12 Synchronous DRAM Timings
Table 6–28 and Table 6–29 assume testing over recommended operating conditions (see Figure 6–23
through Figure 6–29).
NO.
6 tsu(DV-SCLKH)
7 th(SCLKH-DV)
Table 6–28. Synchronous DRAM Timing Requirements
Setup time, read data valid before SDRAM_CLK high
Hold time, read data valid after SDRAM_CLK high
MIN
4.5
2
MAX
UNIT
ns
ns
Table 6–29. Synchronous DRAM Switching Characteristics
NO.
PARAMETER
1 td(SCLKH-CSV)
2 td(SCLKH-DQMV)
3 td(SCLKH-DQMIV)
4 td(SCLKH-AV)
5 td(SCLKH-AIV)
8 td(SCLKH-CASV)
9 td(SCLKH-DV)
10 td(SCLKH-DIV)
11 td(SCLKH-WEV)
12 td(SCLKH-RASV)
Delay time, SDRAM_CLK high to chip select valid
Delay time, SDRAM_CLK high to byte enable valid
Delay time, SDRAM_CLK high to byte enable invalid
Delay time, SDRAM_CLK high to address valid
Delay time, SDRAM_CLK high to address invalid
Delay time, SDRAM_CLK high to SDRAM_CAS valid
Delay time, SDRAM_CLK high to data valid
Delay time, SDRAM_CLK high to data invalid
Delay time, SDRAM_CLK high to SDRAM_WE valid
Delay time, SDRAM_CLK high to, SDRAM_RAS valid
READ
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
11
11
11
11
11
11
11
11
11
11
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDRAM_CLK
CSn
SDRAM_DQM[3:0]
SDRAM_A[R:0]^†
SDRAM_A[C:0]^†
SDRAM_A[10]^†
DATA[31:00]
1
2
3
BE1
BE2
BE3
BE4
4
5
Bank
4
5
Column
4
5
6
7
D1
D2
D3
D4
SDRAM_RAS
SDRAM_CAS
8
8
SDRAM_WE
† _{The values for R and C depend on the particular size of the SRAMs used.}
Figure 6–23. SDRAM Read Command (CAS Latency 3)
72 SPRS180C
June 2001 – Revised December 2002