TMS320LF2407_08 Datasheet, PDF (80/116 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2407, TMS320LF2406, TMS320LF2402
DSP CONTROLLERS
SPRS094I − APRIL 1999 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
SPICLK
(Clock Polarity = 0)
SPICLK
(Clock Polarity = 1)
1
2
3
4
5
SPISIMO
Master Out Data Is Valid
SPISOMI
8
9
Master In Data
Must Be Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active}
until the SPI communication stream is complete.
Figure 35. SPI Master Mode External Timing (Clock Phase = 0)
80
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