UCC5696 Datasheet, PDF (8/12 Pages) Texas Instruments – 27 LINE LVD ONLY SCSI TERMINATOR FOR SPI-5

UCC5696
SLVS406B – JUNE 2002 – REVISED JUNE 2003
APPLICATION INFORMATION
I²C interface
The two-wire serial interface is used to access the terminator and to independently adjust both the differential
impedance and the differential bias current. This interface consists of one clock line, (SCL), and one serial data
line, (SDA).
The access cycle consists of the following and is shown in Figure 2:
1. A start condition
2. A slave address cycle
3. A data cycle
4. A stop condition
SCL
SDA
Start Condition (S)
Stop Condition (P)
Figure 1. I²C Start and Stop Condition
The start and stop conditions are shown in Figure 1. The high-to-low transition of SDA while SCL is high defines
the start condition. The low-to-high transition of SDA while SCL is high, defines the stop condition. The start and
stop conditions are initiated by the master device.
Each cycle, data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the
receiving device. During the acknowledge clock pulse (the ninth clock) the transmitting device must release the
SDA line. The receiving device then pulls down the SDA line so that it remains stable LOW during the HIGH
period of the acknowledge clock pulse.
slave address
The slave address of the UCC5696 terminator has 8 bits consisting of 7 bits of address along with 1 bit, the LSB,
reserved for the read/write information (1 for read and 0 for write). The 7-bit address is fully programmable.
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