TSB41BA3D Datasheet, PDF (8/59 Pages) Texas Instruments – IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
Table 1. Terminal Functions (continued)
TERMINAL
NAME
TYPE
PFP
NO.
I/O
DESCRIPTION
LCLK_PMC
CMOS
7
I _{Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to}
the PHY. On hardware reset, this terminal is sampled to determine the power management
control (PMC) mode.
LCLK_PMC
LPS BMODE Mode
H
L
H
No LLC (PMC mode)
n/c ⁽¹⁾
lps
L
Legacy LLC
LCLK_PMC ⁽²⁾
lps
H
Beta LLC
LPS
LREQ
PCLK
PD
PINT
In PMC mode, because no LLC is attached, the data lines (D7–D0) are available to indicate
power states. In PMC mode, the following signals are output:
• D0—port 0 cable-power disable (see Note)
• D1—port 1 cable-power disable (port in sleep or disabled)
• D2—port 2 cable-power disable (port in sleep or disabled)
• D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits D0–D2
• D3–D5 and D7 are reserved for future use.
NOTE: The cable-power disable is asserted when the port is either:
• Hard-disabled (both the disabled and hard-disabled bits are set)
• Sleep-disabled (both the disabled and sleep_enable bits are set)
• Disconnected
• Asleep
• Connected in DS mode, but nonactive (that is, suspended or disabled)
Otherwise, the cable-power disable output is deasserted (that is, cable power is enabled)
when the port is dc-connected or active. A bus holder is built into this terminal.
CMOS
80
I _{Link power status input. This terminal monitors the active/power status of the link-layer}
controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be
connected to either the V_DD supplying the LLC through an approximately 1-kΩ resistor or to
a pulsed output which is active when the LLC is powered. A pulsed signal must be used
when an isolation barrier exists between the LLC and PHY (see Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for more than an
LPS_RESET time (~2.6 µs), and is considered active otherwise (that is, asserted steady
high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high
for at least 22 ns to be observed as high by the PHY.
When the TSB41BA3D detects that the LPS input is inactive, it places the PHY-LLC
interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D
(D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the
PCLK output remains active. If the LPS input remains low for more than an LPS_DISABLE
time (~26 µs), then the PHY-LLC interface is put into a low-power disabled state in which
the PCLK output is also held inactive.
The LLC state that is communicated in the self-ID packet is considered active only if both
the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is
communicated in the self-ID packet is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.
CMOS
3
I LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3D.
A bus holder is built into this terminal.
CMOS
5
O PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the
LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK
output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC
when the PHY-link interface is in legacy 1394a-2000 (BMODE input deasserted).
CMOS
77
I Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD
input high also activates an internal pulldown on the RESET terminal to force a reset of the
internal control logic.
CMOS
1
O PHY interrupt. The PHY uses this output to serially transfer status and interrupt information
to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this
terminal.
(1) Internal pulldown on LCLK_PMC
(2) LCLK_PMC from LLC normally low during reset
8
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