TPS54290_1 Datasheet, PDF (8/35 Pages) Texas Instruments – 1.5-A/2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET

TPS54290, TPS54291, TPS54292
SLUS973 – OCTOBER 2009
DEVICE INFORMATION
HTSSOP (PWP)
(Top View)
PVDD1 1
BOOT1 2
SW1 3
PGND1 4
EN1 5
EN2 6
FB1 7
COMP1 8
Thermal Pad
(bottom side)
16 PVDD2
15 BOOT2
14 SW2
13 PGND2
12 BP
11 GND
10 FB2
9 COMP2
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PIN
NAME
NO.
BOOT1
2
BOOT2
15
BP
12
EN1
5
EN2
6
FB1
7
FB2
10
COMP1
8
COMP2
9
PGND1
4
PGND2
13
GND
11
PVDD1
1
PVDD2
16
SW1
3
SW2
14
Thermal Pad
PIN FUNCTIONS
I/O
DESCRIPTION
Input supply to the high-side gate driver for Output1. Connect a 22 nF to 68 nF capacitor from this pin to
I
SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON
during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5
Ω) may be placed in series with the bootstrap capacitor.
Input supply to the high-side gate driver for Output2. Connect a 22 nF to 68 nF capacitor from this pin to
I
SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON
during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5
Ω) may be placed in series with the bootstrap capacitor.
–
Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR 4.7-µF (10-µF
preferred) ceramic capacitor.
Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled
I
(high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to
begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass
the enable function.
Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled
I
(high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft-start of Output2 to
begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass
the enable function.
I Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx
to regulate the voltage at this pin to the internal 0.8 V reference. A series resistor divider from Outputx to
I _{ground, with the center connection tied to this pin, determines the value of the regulated output voltage.}
O _{Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to}
O ^GND.
– _{Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal}
– ^{logic circuits.}
– Analog ground pin for the device.
I
Power input to the Output1 high-side MOSFET only. This pin should be locally bypassed to PGND1 with a
low ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together.
The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins
I
and provides power to the Output2 high-side MOSFET. This pin should be locally bypassed to PGND2 with
a low ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the
device when PVDD2 is greater than 4.2 V.
O Source (switching) output for Output1 PWM.
O Source (switching) output for Output2 PWM.
– This pad must be tied externally to a ground plane.
8
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