TPS23754 Datasheet, PDF (8/41 Pages) Texas Instruments – High Power/High Efficiency PoE Interface and DC/DC Controller

TPS23754
TPS23754-1
TPS23756
SLVS885B – OCTOBER 2008 – REVISED MAY 2009 ....................................................................................................................................................... www.ti.com
PIN DESCRIPTION
Refer to Figure 1 for component reference designators (R_CS for example), and the Electrical Characteristics table
for values denoted by reference (V_CSMAX for example). Electrical Characteristic values take precedence over any
numerical values used in the following sections.
APD
APD forces power to come from an external adapter connected from V_DD1 to RTN by opening the hotswap
switch, disabling the CLS output (see PPD pin description), and enabling the T2P output. A resistor divider is
recommended on APD when it is connected to an external adapter. The divider provides ESD protection,
leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the
adapter output voltage is high enough that it can support the PD before the PoE current is cut off.
Select the APD divider resistors per Equation 1 where V_ADPTR-ON is the desired adapter voltage that enables the
APD function as adapter voltage rises.
( ) ^R_APD1 ^{= R}_APD2 ^{´ V}_{ADPTR_ON} ^{- V}_APDEN ^V_APDEN
( ) V_{ADPTR_OFF}
=
R_APD1 + R_APD2
R _APD2
´
V_APDEN - V_APDH
(1)
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to ARTN when not used.
BLNK
Blanking provides an interval between GATE going high and the current-control comparators on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparators are active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a
more accurate, programmable blanking period. The relationship between the desired blanking period and the
programming resistor is defined by Equation 2.
R_BLNK (kW) = t_BLNK (ns)
(2)
Place the resistor adjacent to the BLNK pin when it is used.
CLS
A resistor from CLS to V_SS programs the classification current per the IEEE standard. The PD power ranges and
corresponding resistor values are listed in Table 1. The power assigned should correspond to the maximum
average power drawn by the PD during operation.
High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle. The TPS23754
presents the same (resistor programmed) class each cycle per the standard.
CLASS
0
1
2
3
4
POWER AT PD
MINIMUM
(W)
MAXIMUM
(W)
0.44
12.95
0.44
3.84
3.84
6.49
6.49
12.95
12.95
25.5
Table 1. Class Resistor Selection
RESISTOR
(Ω)
NOTES
1270
243
137
90.9
63.4
Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
Not allowed for IEEE 802.3-2005. Use to indicate a Type 2 PD (high power) per
IEEE 802.3at.
8
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