TLC0834C Datasheet, PDF (8/15 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
analog and converter section
PARAMETER
VIC
Common-mode input voltage
II(stdby) Standby input current (see Note 4)
ri(REF) Input resistance to REF
On channel
Off channel
On channel
Off channel
TEST CONDITIONS†
See Note 3
VI = 5 V
VI = 0
VI = 0
VI = 5 V
MIN
– 0.05
to
VCC+ 0.05
1.3
TYP‡
2.4
MAX
1
–1
–1
1
5.9
UNIT
V
µA
kΩ
total device
PARAMETER
MIN TYP‡ MAX UNIT
ICC Supply current
0.6 1.25 mA
† _{All parameters are measured under open-loop conditions with zero common-mode input voltage.}
‡ _{All typical values are at VCC = 5 V, TA = 25°C.}
NOTES: 3. When channel IN – is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are
two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC.Care must be taken during
testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause the input
diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 5-V input range requires a minimum VCC of
4.950 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state condition.
operating characteristics, V_CC = 5 V, f_clock = 250 kHz, t_r = t_f = 20 ns, T_A = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS§
MIN TYP MAX UNIT
Supply-voltage variation error
Total unadjusted error (see Note 5)
Common-mode error
VCC = 4.75 V to 5.25 V
Vref = 5 V, TA = MIN to MAX
Differential mode
± 1/16 ± 1/4 LSB
± 1 LSB
± 1/16 ± 1/4 LSB
tpd
Propagation delay time, output
data after CLK↓ (see Note 6) (see Figure 2)
MSB-first data
LSB-first data
CL = 100pF
1500
ns
600
tdis
Output disable time, DO or SARS after CS↑ (see Figure 3)
CL = 10 pF, RL = 10 kΩ
CL = 100 pF, RL = 2 kΩ
250
ns
500
tconv Conversion time (multiplexer-addressing time not included)
8
clock
periods
§ _{All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the}
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time.
2–8
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