TL7702-705-733B Datasheet, PDF (8/9 Pages) Texas Instruments – SUPPLY-VOLTAGE SUPERVISORS

TL7702B, TL7705B, TL7733B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037L – SEPTEMBER 1989 – REVISED MAY 2002
APPLICATION INFORMATION
VS
Reset Input
(from system)
0.1 µF
8
7
VCC
5
SENSE RESET
2
RESIN
1
REF
RT ₃
6
CT
RESET
(see text)
GND
CT
4
System Supply
10 kΩ
To System
RESET
To System
RESET
10 kΩ
Figure 8. System Reset Controller With Undervoltage Sensing
When the TL770xB SENSE terminal is used to monitor V_CC, a current-limiting resistor in series with C_T is
recommended. During normal operation, the timing capacitor is charged by the onboard current source to
approximately V_CC or an internal voltage clamp (≈7.1-V zener), whichever is less. When the circuit is then subjected
to an undervoltage condition during which V_CC is rapidly slewed down, the voltage on CT exceeds that on V_CC. This
forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when V_CC drops
below V_(CT), not when V_SENSE falls below V_T–.
Texas Instruments performs a 100% electrical screen to verify that the outputs do not switch with 1 mA forced into
the CT terminal. Adding the external resistor, R_T, prevents false triggering. Its value is calculated as follows:
* _* V_(CT) V_T
R_T
Where:
V_(CT)
V_T–
R_T
= V_CC or 7.1 V, whichever is less
= 4.55 V (nom)
= value of series resistor required
For V_CC = 5 V:
* t 5 4.55
R_T
1 mA
Therefore,
u W R_T 450
Using a 20%-tolerance resistor, R_T should be greater than 560 Ω.
Adding this series resistor changes the duration of the reset pulse by no more than 10%. R_T extends the discharge
of C_T, but also skews the V_(CT) threshold. These effects tend to cancel one another. The precise percentage change
can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration
of the supply-voltage fault condition.
Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used.
This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an
undefined state or delay system reset.
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