SN74AVC16827 Datasheet, PDF (8/13 Pages) Texas Instruments – 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES176I – DECEMBER 1998 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
V_CC = 2.5 V ± 0.2 V
From Output
Under Test
C_L = 30 pF
(see Note A)
500 Ω ^S1
500 Ω
2 × V_CC
Open
GND
TEST
t_pd
t_PLZ/t_PZL
t_PHZ/t_PZH
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S1
Open
2 × V_CC
GND
LOAD CIRCUIT
Timing
Input
Data
Input
V_CC/2
V_CC
0V
t_su
t_h
V_CC/2
V_CC
V_CC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
t_PLH
Output
V_CC/2
V_CC
V_CC/2
0V
t_PHL
V_CC/2
V_CC/2
V_OH
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Input
t_w
V_CC/2
V_CC
V_CC/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Control
(low-level
enabling)
V_CC/2
V_CC
V_CC/2
0V
t_PZL
Output
Waveform 1
S1 at 2 × V_CC
(see Note B)
V_CC/2
t_PLZ
V_CC
V_OL + 0.15 V
V_OL
t_PZH
t_PHZ
Output
Waveform 2
S1 at GND
(see Note B)
V_CC/2
V_OH
V_OH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, t_r ≤ 2 ns, t_f ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PLH and t_PHL are the same as t_pd.
Figure 4. Load Circuit and Voltage Waveforms
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