SN54ABT16823 Datasheet, PDF (8/9 Pages) Texas Instruments – 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
7V
S1
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
LOAD CIRCUIT
tw
Input 1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Timing Input
3V
Data Input
0V
3V
1.5 V
0V
tsu
th
3V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
3V
1.5 V
0V
tPLH
Output
tPHL
Output
1.5 V
1.5 V
tPHL
VOH
1.5 V
VOL
tPLH
1.5 V
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
tPZL
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZH
1.5 V
tPLZ
1.5 V
tPHZ
1.5 V
3V
1.5 V
0V
3.5 V
VOL + 0.3 V _VOL
VOH – 0.3 V ^VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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