DS90C032TMX Datasheet, PDF (8/18 Pages) Texas Instruments – DS90C032 LVDS Quad CMOS Differential Line Receiver

DS90C032
SNLS094D – JUNE 1998 – REVISED APRIL 2013
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quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the
amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific
application. In applications in low noise environments, they may choose to use a very small bias if any. For
applications with less balanced interconnects and/or in high noise environments they may choose to boost
failsafe further. TIs LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe
biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This
is selected to be close to the nominal driver offset voltage (V_OS). Thus when switching between driven and
un-driven states, the common-mode modulation on the bus is held to a minimum.
For additional Failsafe Biasing information, please refer to Application Note AN-1194 (SNLA051) for more
detail.
The footprint of the DS90C032 is the same as the industry standard 26LS32 Quad Differential (RS-422)
Receiver.
Pin Descriptions
Pin No. (SOIC)
2, 6, 10, 14
1, 7, 9, 15
3, 5, 11, 13
4
12
16
8
Name
R_IN+
R_IN−
R_OUT
EN
EN*
V_CC
GND
Description
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
Ground pin
8
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