CDCR81 Datasheet, PDF (8/13 Pages) Texas Instruments – DIRECT RAMBUSE CLOCK GENERATOR

CDCR81
DIRECT RAMBUS™ CLOCK GENERATOR
SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999
state transition latency specifications (continued)
t(ON)
t(DISTLOCK)
PARAMETER
Minimum time in normal mode (STOPB = 1)
before re-entering CLKSTOP (STOPB = 0)
Time from when CLK/CLKB output is settled to
when the phase error between SYNCLKN and
PCLKM falls within t(ERR-PD)
FROM TO
Normal
CLK
stop
TEST
CONDITIONS
MIN
TYP†
MAX
UNIT
100
ms
Un-
locked
Locked
5 ms
CLK
CLKB
PARAMETER MEASUREMENT INFORMATION
68 Ω, ±5%
10 pF
39 Ω, ±5%
RT = 28 Ω
68 Ω, ±5%
39 Ω, ±5%
100 pF
10 pF
RT = 28 Ω
Figure 1. Test Load and Voltage Definitions (V_O(STOP), V_O(X), V_O, V_OH, V_OL)
CLK
CLKB
tc1
tc2
Cycle-to-cycle jitter = | tc1 – tc2| over 10000 consecutive cycles
Figure 2. Cycle-to-Cycle Jitter
tc3
tc4
Cycle-to-cycle jitter = | tc3 – tc4| over 10000 consecutive cycles
Figure 3. Short Term Cycle-to-Cycle Jitter over 4 Cycles
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