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CD54HC40103 Datasheet, PDF (8/14 Pages) Texas Instruments – High-Speed CMOS Logic 8-Stage Synchronous Down Counters
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CD54HC40103, CD74HC40103, CD74HCT40103
Test Circuits and Waveforms
tr
tf
CP
tPHL
90%
10%
tW
1/fMAX
TC 10%
90%
tTHL
INPUT LEVEL
VS
GND
tPLH
VS
tTLH
FIGURE 2.
tW
MR
VS
INPUT LEVEL
GND
tREM
CP
VS INPUT LEVEL
GND
FIGURE 3.
tf
10%
TE
90%
tPHL
10%
TC
90%
tTHL
tf
INPUT LEVEL
VS
tPLH
VS
tTLH
FIGURE 4.
MR
VS
tSU
th
CP
VS
INPUT LEVEL
GND
INPUT LEVEL
GND
FIGURE 5.
INPUTS
P0 - P7
PE
CP
VALID
VS
th
tSU
VS
tSU
th
VS
tREC
INPUT LEVEL
GND
INPUT LEVEL
GND
INPUT LEVEL
GND
TE
OR
VS
PE
tSU
th
CP
VS
INPUT LEVEL
GND
INPUT LEVEL
GND
trCL
CLOCK
90%
10%
FIGURE 6.
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
FIGURE 7.
tfCL = 6ns
1.3V
0.3V
1.3V
tWL
+
tWH
=
I
fCL
3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 8. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 9. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
8
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