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BQ4850Y Datasheet, PDF (8/16 Pages) Texas Instruments – RTC Module With 512Kx8 NVSRAM | |||
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bq4850Y
AC Test Conditions
Parameter
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
Test Conditions
0V to 3.0V
5 ns
1.5 V (unless otherwise specified)
See Figures 4 and 5
Figure 4. Output Load A
Figure 5. Output Load B
Read Cycle (TA = TOPR, VCCmin ⤠VCC ⤠VCCMAX)
Symbol
Parameter
tRC
Read cycle time
tAA
Address access time
tACE
Chip enable access time
tOE
Output enable to output valid
tCLZ
Chip enable to output in low Z
tOLZ
Output enable to output in low Z
tCHZ
Chip disable to output in high Z
tOHZ
Output disable to output in high Z
tOH
Output hold from address change
â85
Min. Max.
85
-
-
85
-
85
-
45
5
-
0
-
0
35
0
25
10
-
Unit
Conditions
ns
ns Output load A
ns Output load A
ns Output load A
ns Output load B
ns Output load B
ns Output load B
ns Output load B
ns Output load A
Aug. 1996
8
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