ADS931 Datasheet, PDF (8/16 Pages) Burr-Brown (TI) – 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER

THEORY OF OPERATION
The ADS931 is a high-speed sampling A/D converter that
utilizes a pipeline architecture. The fully differential topol-
ogy and digital error correction guarantee 8-bit resolution.
The track-and-hold circuit is shown in Figure 1. The switches
are controlled by an internal clock which has a non-overlap-
ping two phase signal, φ1 and φ2. At the sampling time the
input signal is sampled on the bottom plates of the input
capacitors. In the next clock phase, φ2, the bottom plates of
the input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time the
charge redistributes between C_I and C_H, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. In the
normal mode of operation, the complementary input is tied
to the common-mode voltage. In this case, the track-and-
hold circuit converts a single-ended input signal into a fully
differential signal for the quantizer. Consequently, the input
signal gets amplified by a gain or two, which improves the
signal-to-noise performance. Other parameters such as small-
signal and full-power bandwidth, and wideband noise are
also defined in this stage.
Op Amp
Bias
V_CM
φ1
φ1
C_H
IN
φ1 _φ2
IN
(Opt.) ^φ1
C_I
φ1
C_I
φ1
φ2
C_H
φ2
φ1
Input Clock (50%)
Op Amp
V_CM
Bias
Internal Non-overlapping Clock
φ1
φ2
φ1
OUT
OUT
FIGURE 1. Input Track-And-Hold Configuration with
Timing Signals.
IN
Input
T/H
STAGE 1 ⁺
Σ^–
2-Bit
Flash
x2
2-Bit
DAC
STAGE 2 +
Σ^–
2-Bit
Flash
x2
2-Bit
DAC
Digital Delay
Digital Delay
STAGE 6 +
Σ–
x2
2-Bit
Flash
2-Bit
DAC
STAGE 7
2-Bit
Flash
FIGURE 2. Pipeline A/D Architecture.
8
Digital Delay
Digital Delay
B1 (MSB)
B2
B3
B4
B5
B6
B7
B8 (LSB)
ADS931
SBAS060A