TMS320LF2407A_07 Datasheet, PDF (79/134 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
Input transition times are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
A
A[15:0]
Cl
XTAL1/CLKIN
CO
CLKOUT
D
D[15:0]
INT
XINT1, XINT2
MS
Memory strobe pins IS, DS, or PS
R
READY
RD
Read cycle or RD
RS
RESET pin RS
W
Write cycle or WE
Lowercase subscripts and their meanings:
a
access time
c
cycle time (period)
d
delay time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
Letters and symbols and their meanings:
H
High
L
Low
V
Valid
X
Unknown, changing, or don’t care level
Z
High impedance
general notes on timing
All output signals from the 240xA devices (including CLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this data sheet.
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