TVP5146PFP Datasheet, PDF (77/100 Pages) Texas Instruments – NTSC/PAL SECAM 4X10 BIT DIGITAL VIDEO DECODER WITH MACROVISION

2.11.83 Interrupt Raw Status 0 Register
Subaddress F0h
Read only
7
6
FIFO THRS
TTX
5
WSS
4
VPS
3
2
1
0
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed, unmasked
0 = Not passed
1 = Passed
TTX: Teletext data available unmasked
0 = Not available
1 = Available
WSS: WSS data available unmasked
0 = Not available
1 = Available
VPS: VPS data available unmasked
0 = Not available
1 = Available
VITC: VITC data available unmasked
0 = Not available
1 = Available
CC F2: CC field 2 data available unmasked
0 = Not available
1 = Available
CC F1: CC field 1 data available unmasked
0 = Not available
1 = Available
Line: Line number interrupt unmasked
0 = Not available
1 = Available
See also the interrupt raw status 1 register at subaddress F1h (see Section 2.11.84).
The host interrupt raw status 0 and 1 registers represent the interrupt status without applying mask bits.
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