TMS320F28022 Datasheet, PDF (77/104 Pages) Texas Instruments – Piccolo Microcontrollers

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V_DDIO, V_DDA
(3.3 V)
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A – NOVEMBER 2008 – REVISED DECEMBER 2008
V_DD (1.8 V)
INTOSC1
t_INTOSCST
X1/X2
XCLKOUT
XRS
Address/Data/
Control
(Internal)
Boot-Mode
Pins
t_OSCST
t_w(RSL1)
(A)
OSCCLK/8
User-code dependent
Address/data valid, internal boot-ROM code execution phase
t_d(EX)
t_{h(boot-mode)(B)}
GPIO pins as input
Boot-ROM execution starts
User-code execution phase
User-code dependent
Peripheral/GPIO function
Based on boot code
I/O Pins^(C)
GPIO pins as input (state depends on internal PU/PD)
User-code dependent
A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-6. Power-on Reset
t_h(boot-mode)
t_w(RSL2)
Table 6-10. Reset (XRS) Timing Requirements
Hold time for boot-mode pins
Pulse duration, XRS low on warm reset
MIN
TBD
NOM
8t_c(OSCCLK)
MAX UNIT
cycles
cyclies
Table 6-11. Reset (XRS) Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
t_w(RSL1)
t_w(WDRS)
PARAMETER
Pulse duration, XRS driven by device
Pulse duration, reset pulse generated by
watchdog
TEST CONDITIONS
MIN
TYP
600
512t_c(OSCCLK)
MAX UNIT
µs
cycles
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Electrical Specifications
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