PCI1620 Datasheet, PDF (76/164 Pages) Texas Instruments – DUAL-SOCKET PL CARD AND UITRAMEDIA CONTROLLER

4.14 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates
CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI
offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket
functions, but is accessed on a per-socket basis. See Table 4−4 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Secondary status
Type
RC RC RC RC RC
R
R
RC
R
R
R
R
R
R
R
R
Default 0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Secondary status
16h
Read-only, Read/Clear
0200h
BIT
15
14
13
12
11
10−9
8
7
6
5
4−0
SIGNAL
CBPARITY
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
CB_DPAR
CBFBB_CAP
CB_UDF
CB66MHZ
RSVD
Table 4−4. Secondary Status Register Description
TYPE
FUNCTION
RC
Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data
parity error. Write a 1 to clear this bit.
Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI1620 does not
RC _{assert the CSERR signal. Write a 1 to clear this bit.}
RC
Received master abort. This bit is set when a cycle initiated by the PCI1620 on the CardBus bus is
terminated by a master abort. Write a 1 to clear this bit.
RC
Received target abort. This bit is set when a cycle initiated by the PCI1620 on the CardBus bus is
terminated by a target abort. Write a 1 to clear this bit.
Signaled target abort. This bit is set by the PCI1620 when it terminates a transaction on the CardBus bus
RC _{with a target abort. Write a 1 to clear this bit.}
R
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI1620 asserts this signal at a medium speed.
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
RC
a. CPERR was asserted on the CardBus interface.
b. The PCI1620 was the bus master during the data parity error.
c. The parity error response enable bit (bit 0) is set in the bridge control register (offset 3Eh, see
Section 4.25).
Fast back-to-back capable. The PCI1620 cannot accept fast back-to-back transactions; therefore, this bit
R
is hardwired to 0.
R
User-definable feature support. The PCI1620 does not support user-definable features; therefore, this bit
is hardwired to 0.
R
66-MHz capable. The PCI1620 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, this bit is hardwired to 0.
R These bits return 0s when read.
4−8